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| (R) LCP150S PROGRAMMABLE TRANSIENT VOLTAGE SUPPRESSOR FOR SLIC PROTECTION Application Specific Discretes A.S.D.TM FEATURES DUAL PROGRAMMABLE TRANSIENT SUPPRESSOR HIGH SURGE CURRENT CAPABILITY. - IPP = 50A, 10/1000 s. - IPP = 60 A, 5/310 s. - IPP = 150 A, 2/10 s. HOLDING CURRENT = 150 mA min. LOW GATE TRIGGERING CURRENT : IGT = 15 mA max. DESCRIPTION SIP 4 SCHEMATIC DIAGRAM This device has been especially designed to protect a subscriber line card interface (SLIC) against transient overvoltage. Positive overloads are clipped with two diodes, while negative surges are suppressed by two protection thyristors, their breakdown voltage being is referencedto the -Vbat. This component presents a very low gate triggering current (I GT) in order to reduce the current consumption on the PC board during the firing phase. COMPLIES WITHTHE FOLLOWING STANDARDS: CCITT - K20 VDE 0433 VDE 0878 FCC part 68 10/700s 5/310s 10/700s 5/200s 1.2/50s 1/20s 2/10s 2/10s 1kV 25A 2kV 50A 1.5kV 40A 2.5kV 150A(*) 2.5kV 150A(*) 1kV 50A(*) 1kV 25A CONNECTION DIAGRAM BELLCORE TR-NWT-001089 : 2/10s 2/10s 10/1000s 10/1000s CNET 0.5/700s 0.2/310s (*) with series resistors or PTC. TM: ASD is trademarks of SGS-THOMSON Microelectronics. February 1998 - Ed: 3 1/6 LCP150S ABSOLUTE MAXIMUM RATINGS (Tamb = 25 C) Symbol IPP Parameter Peak pulse current (see note 1) 10/1000 s 5/320 s 2/10 s tp = 10 ms t=1s Value 50 60 150 25 8 2 - 100 - 80 - 55 to + 150 150 260 Unit A ITSM Non repetitivesurge peakon-statecurrent F = 50 Hz A IGSM VMLG VMGL Tstg Tj TL Maximum gate current (half sine wave tp = 10 ms) Maximum Voltage LINE/GND Maximum Voltage GATE/LINE Storage temperature range Maximum operating junction temperature Maximum lead temperature for soldering during 10s A V C C C Note 1: Pulse waveform 10/1000 s tr = 10 s 5/320 s tr = 5 s 2/10 s tr = 2 s, % I PP 100 tp = 1000 s tp = 320 s tp = 10 s 50 0 tr tp t THERMAL RESISTANCE Symbol Rth (j-a) Junction-to-ambient Parameter Value 80 Unit C/W 2/6 (R) LCP150S ELECTRICAL CHARACTERITICS (Tamb = 25C, unless otherwise specified) Symbol IGT IH IR IRG VR VF VGT VFP VSGL Vgate VLG C Parameter Gate Trigger Current Holding Current Reverse Leakage Current LINE/GND Reverse Leakage Current GATE/LINE Reverse Voltage LINE/GND Forward Voltage LINE/GND Gate Trigger Voltage Peak Forward Voltage LINE/GND Dynamic Switching Voltage GND/LINE GATE/GND Voltage LINE/GND Voltage Off State Capacitance LINE/GND Ipp IH VF VSGL VR IR VGL I IF 1 - PARAMETERS RELATED TO THE DIODE LINE/GND Symbol VF VFP Test Conditions Square pulse, Tp = 500 s, IF = 5 A Ipp = 40 A, 10/1000s. Max. 3 15 Unit V V 2 - PARAMETERS RELATED TO PROTECTION THYRISTOR Symbol IGT IH VGT IRG VSGL VGND/LINE = -48 V VGATE= -48 V at IGT Tc = 25C Tc = 70C VGATE= -48 V VRG = -75 V VRG = -75 V Note 2 Tests Conditions Note 2 Min. 0.2 150 Max. 15 2.5 5 50 - 63 Unit mA mA V A A V 3 - PARAMETERS RELATIVE TO DIODE AND PROTECTION THYRISTOR Symbol IR C Tc = 25C Tc = 70C VR = - 3 V VR = - 48 V Tests Conditions -1 < VGL < -Vbat -1 < VGL < -Vbat F < 1MHz F < 1MHz VR = - 85 V VR = - 85 V Min. Max. 5 50 150 80 Unit A A pF pF Note 2 : See test circuit for IH and VSGL. 3/6 (R) LCP150S Fig. 1 : Surge peak current versus overload duration (typical values). ITSM(A) 30 Tj initial = 25C 25 20 15 10 5 t(s) 0 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3 FUNCTIONAL HOLDING CURRENT (IH) TEST CIRCUIT = GO - NOGO TEST. R Vbat = - 48V VSGL - Vpp Ipp = 10A,10/1000 s This is a GO-NOGO Test which allows to confirm the holding current (IH) level in a functional test circuit. This test can be performedif the reference test circuit can't be implemented. TEST PROCEDURE : 1) Adjust the current level at the IH value by short circuiting the AK of the D.U.T. 2) Fire the D.U.T with a surge Current : Ipp = 10A , 10/1000 s. 3) The D.U.T will come back to the OFF-State within a duration of 50 ms max. The VSGL is measured just before firing 4/6 (R) LCP150S APPLICATION CIRCUIT Typical SLIC Protection Concept. RING GENERATOR - VBAT PTC LINE A T E S T R E L A Y S LINE B RING RELAY 220 nF SLIC PTC THBT200S LCP150S FUNCTIONAL DESCRIPTION LINE A PROTECTION: - For positive surges versus GND, the diode D1 will conduct. - For negative surges versus GND, the protection device P1 will trigger at a voltage fixed by the -VBAT reference. LINE B PROTECTION: - For surges on Line B, the operating mode is the same , D2 or P2 is activated. A capacitor (C = 220nF) can be added close to the gate of the LCP15xx, in order to speed up the triggering. 5/6 (R) LCP150S MARKING : Logo, Date Code, LCP150S. ORDER CODE LCP 150 S LINE CARD PROTECTION HOLDING CURRENT : 150 mA PACKAGE S = SIP4 PLASTIC PACKAGE MECHANICAL DATA SIP 4 DIMENSIONS REF. A a1 B b1 b2 c1 e e3 I L Z PACKAGING : Productssuppliedin antistatic tubes. WEIGHT : 0.55g Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. Millimetres Inches Min. Typ. Max. Min. Typ. Max. 7.10 2.80 10.15 0.50 1.35 0.38 2.54 7.62 10.50 3.30 1.50 0.130 0.059 1.75 0.053 0.50 0.015 0.100 0.200 0.413 0.020 0.069 0.020 0.110 0.400 0.280 (c) 1998 SGS-THOMSON Microelectronics - Printed in Italy - All rights reserved. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 6/6 (R) |
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